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ltc3783 1 3783fb typical application features applications description pwm led driver and boost, flyback and sepic controller the ltc ? 3783 is a current mode led driver and boost, ? yback and sepic controller that drives both an n-channel power mosfet and an n-channel load pwm switch. when using an external load switch, the pwmin input not only drives pwmout, but also enables controller gate switch- ing and error ampli? er operation, allowing the controller to store load current information while pwmin is low. this feature (patent pending) provides extremely fast, true pwm load switching with no transient overvoltage or undervoltage issues; led dimming ratios of 3000:1 can be achieved digitally, avoiding the color shift normally associated with led current dimming. the fbp pin allows analog dimming of load current, further increasing the effective dimming ratio by 100:1 over pwm alone. in applications where output load current must be returned to v in , optional constant current/constant voltage regula- tion controls either output (or input) current or output voltage and provides a limit for the other. i lim provides a 10:1 analog dimming ratio. for low- to medium-power applications, no r sense mode can utilize the power mosfets on-resistance to eliminate the current-sense resistor, thereby maximizing ef? ciency. the ics operating frequency can be set with an external resistor over a 20khz to 1mhz range and can be synchro- nized to an external clock using the sync pin. the ltc3783 is available in the 16-lead dfn and tssop packages. 350ma pwm led boost application n true color pwm tm delivers constant color with 3000:1 dimming ratio n fully integrated load fet driver for pwm dimming control of high power leds n 100:1 dimming from analog inputs n wide fb voltage range: 0v to 1.23v n constant current or constant voltage regulation n low shutdown current: i q = 20a n 1% 1.23v internal voltage reference n 2% run pin threshold with 100mv hysteresis n programmable operating frequency (20khz to 1mhz) with one external resistor n synchronizable to an external clock up to 1.3f osc n internal 7v low dropout voltage regulator n programmable output overvoltage protection n programmable soft-start n can be used in a no r sense tm mode for v ds < 36v n 16-lead dfn and tssop packages n high voltage led arrays n telecom power supplies n 42v automotive systems n 24v industrial controls n ip phone power supplies , lt, ltc and ltm are registered trademarks of linear technology corporation. true color pwm and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. typical waveforms ltc3783 1m run pwmin i th ss v ref fbp fbn freq sync v in ov/fb pwmout i lim gate sense intv cc gnd led* string v in 6v to 16v (< total v f of leds) gnd m1 m1, m2: siliconix si4470ey 10f s 2 zetex zlls1000 m2 c out 10f v out <25v *lumileds lhxl-bw02 3783 ta01a 0.1f 10k 6k 105k 10f 2.2h 4.7f 0.05 237k 12.4k 0.3 v pwmin 5v/div i l 2.5a/div i led 0.5a/div v out 0.2v/div ac coupled 1s/div 3783 ta01b
ltc3783 2 3783fb absolute maximum ratings v in , sense, fbp, fbn voltages ................. ?0.3v to 42v intv cc voltage ............................................ ?0.3v to 9v intv cc output current .......................................... 75ma gate output current ................................. 50ma (rms) pwmout output current .......................... 25ma (rms) v ref ouput current ................................................. 1ma gate, pwmout voltages .......?0.3v to (v intvcc + 0.3v) i th , i lim , ss voltages ............................... ?0.3v to 2.7v run, sync, pwmin voltages..................... ?0.3v to 7v freq, v ref , ov/fb voltages...................... ?0.3v to 1.5v (note 1) 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 run i th ov/fb ss sense v in intv cc gate fbn fbp i lim v ref freq sync pwmin pwmout top view dhd package 16-lead (5mm s 4mm) plastic dfn t jmax = 125c, = = =
ltc3783 3 3783fb symbol parameter conditions min typ max units main control loop/whole system v in input voltage range 3 36 v i q input voltage supply current continuous mode shutdown mode (note 4) v ov/fb = 1.5v, v ith = 0.75v v run = 0v 1.5 20 ma a v run + rising run input threshold voltage 1.348 v v run C falling run input threshold voltage 1.223 1.248 1.273 v v run(hyst) run pin input threshold hysteresis 100 mv i run run pin input current 5na v sense(max) maximum current sense threshold 125 150 180 mv i sense(on) sense pin current (gate high) v sense = 0v 70 a i sense(off) sense pin current (gate low) v sense = 36v 0.2 a i ss soft-start pin output current v ss = 0v -50 a voltage/temperature reference v ref reference voltage l 1.218 1.212 1.230 1.242 1.248 v v i ref max reference pin output current 0.5 ma v ref / v in reference voltage line regulation 3v v in 36v 0.002 0.02 %/v v ref / i ref reference voltage load regulation 0ma i ref 0.5ma 0.2 1.0 %/ma t max overtemperature sd threshold rising 165 c t hyst overtemperature hysteresis 25 c error ampli? er i ov/fb ov/fb pin input current 18 60 na v ov/fb(ov) ov/fb overvoltage lockout threshold v ov/fb(ov) C v ov/fb(nom) in %, v fbp v ref 7% v ov/fb(fb) ov/fb pin regulation voltage 2.5v < v fbp < 36v 1.212 1.230 1.248 v i fbp , i fbn error ampli? er input current 0v v fbp v ref 2.5v < v fbp < 36v C0.4 50 a a v fbp C v fbn error ampli? er offset voltage (note 5) 0v v fbp v ref 2.5v < v fbp 36v (v ilim = v ref ) 2.5v < v fbp 36v (v ilim = 0.123v) C3 100 10 3mv mv mv g m error ampli? er transconductance v fbp v ref 2.5v < v fbp < 36v 1.7 14 mmho mmho a vol error ampli? er open-loop gain 500 v/v oscillator f osc oscillator frequency oscillator frequency range r freq = 20k 250 20 300 350 1000 khz khz d max maximum duty cycle 85 90 97 % f sync /f osc recommended max sync freq ratio f osc = 300khz (note 6) 1.25 1.3 t sync(min) sync minimum input pulse width v sync = 0v to 5v 25 ns t sync(max) sync maximum input pulse width v sync = 0v to 5v 0.8/f osc ns v ih(sync) sync input voltage high level 1.2 v v hyst(sync) sync input voltage hysteresis 0.5 v the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c. v in = 12v, v run = 1.5v, v sync = 0v, v fbp = v ref , r t = 20k, unless otherwise speci? ed. electrical characteristics
ltc3783 4 3783fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3783e is guaranteed to meet performance speci? cations over the 0c to 85c operating temperature range. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3783i is guaranteed to meet performance speci? cations over the full C40c to 125c operating temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 43c/w) for the dfn t j = t a + (p d ? 38c/w) for the tssop the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c. v in = 12v, v run = 1.5v, v sync = 0v, v fbp = v ref , r t = 20k, unless otherwise speci? ed. electrical characteristics symbol parameter conditions min typ max units r sync sync input pull-down resistance 100 k t on(min) minimum on-time with sense resistor, 10mv overdrive no r sense mode 170 300 ns ns low dropout regulator v intvcc intv cc regulator output voltage v ov/fb = 1.5v l 6.5 7 7.5 v uvlo intv cc undervoltage lockout thresholds rising intv cc falling intv cc hysteresis 1.8 2.3 2.1 0.2 2.5 v v v v intvcc v in intv cc line regulation 12v v in 36v 2 6 mv/v v ldo(load) intv cc load regulation 0 i intvcc 10ma C1 C0.1 % v dropout intv cc dropout voltage v in = 7v, i intvcc = 10ma 300 500 mv i intvcc(sd) bootstrap mode intv cc supply current in shutdown v sense = 0v v sense = 7v 25 15 a a gate/pwmout drivers t r(gate) gate driver output rise time c l = 3300pf (note 7) 15 ns t f(gate) gate driver output fall time c l = 3300pf (note 7) 8 ns i pk(gate,rise) gate driver peak current sourcing v gate = 0v 0.5 a i pk(gate,fall) gate driver peak current sinking v gate = 7v 1 a v pwmin pwmin pin input threshold voltages rising pwmin falling pwmin hysteresis 1.6 0.8 0.8 v v v r pwmin pwmin input pull-up resistance 100 k t r(pwmout) pwmout driver output rise time c l = 3300pf (note 7) 30 ns t f(pwmout) pwmout driver output fall time c l = 3300pf (note 7) 16 ns i pk(pwmout,rise) pwmout driver peak current sourcing v pwmout = 0v 0.25 a i pk(pwmout,fall) pwmout driver peak current sinking v pwmout = 7v 0.50 a note 4: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see operation section. note 5: the ltc3783 is tested in a feedback loop which servos v fbn to v fbp = v vref with the i th pin forced to the midpoint of its voltage range (0.3v v ith 1.2v; midpoint = 0.75v). note 6: in a synchronized application, the internal slope compensation is increased by 25%. synchronizing to a signi? cantly higher ratio will reduce the effective amount of slope compensation, which could result in sub- harmonic oscillation for duty cycles greater than 50% note 7 : rise and fall times are measured at 10% and 90% levels.
ltc3783 5 3783fb typical performance characteristics temperature (c) C50 v ref (v) 1.15 1.20 1.25 3783 g01 1.10 1.05 1.00 0 50 100 150 v in (v) 0 v ref (v) 1.229 1.231 40 3783 g02 1.227 1.225 10 20 30 1.235 1.233 i ref (ma) 0 v ref (v) 1.231 1.233 1.235 4 3783 g03 1.229 1.227 1.225 1 2 3 5 v in = 12v v in = 2.5v temperature (c) C75 i q (ma) 0.6 0.8 1.0 75 175 3783 g04 0.4 0.2 0 C25 25 125 1.2 1.4 1.6 v in (v) 0 0 i q (ma) 1.1 1.3 1.4 1.5 20 40 50 2.0 1.9 3783 g05 1.2 10 30 1.6 1.7 1.8 frequency (mhz) 0 0 dynamic i q (ma) 5 10 15 20 30 0.5 1 3783 g06 1.5 25 c l = 3300pf i q(tot) = 1.3ma + q g ? f v in (v) 0 0.6 run thresholds (v) 0.7 0.9 1.0 1.1 1.6 1.3 10 20 3783 g07 0.8 1.4 1.5 1.2 30 40 run high run low temperature (c) C50 run thresholds (v) 1.32 1.34 1.36 150 3783 g08 1.30 1.28 1.22 0 50 100 1.26 1.24 1.40 1.38 run high run low frequency (khz) 10 r t (k) 100 1 100 1000 10000 3783 g09 1 10 1000 v ref vs temperature v ref line regulation v ref load regulation i q vs temperature (pwmin low) i q vs v in (pwmin low) dynamic i q vs frequency run thresholds vs v in run thresholds vs temperature r t vs frequency t a = 25c unless otherwise speci? ed
ltc3783 6 3783fb typical performance characteristics temperature (c) C50 250 frequency (khz) 260 280 290 300 350 320 0 50 3783 g10 270 330 340 310 100 150 temperature (c) C50 v sense (v) 152 156 160 3783 g11 148 144 150 154 158 146 142 140 0 50 100 150 temperature (c) C50 65 i sense (a) 66 68 69 70 75 72 0 50 3783 g12 67 73 74 71 100 150 i intvcc (ma) 0 6.50 6.55 6.80 6.75 6.70 intv cc (v) 6.85 6.90 6.95 7.00 0.02 0.04 0.06 0.08 3783 g13 0.10 0.12 0.14 0.16 v in (v) 0 intv cc (v) 6.80 6.90 7.00 7.05 40 3783 g14 6.70 6.60 6.75 6.85 6.95 6.65 6.55 10 20 30 50 i intvcc (ma) 0 5.0 intv cc (v) 5.4 5.6 5.8 6.0 6.2 6.4 50 100 3783 g15 6.6 6.8 7.0 5.2 150 C50c, C25c, 0c 50c 100c 125c 25c 75c 150c v in (v) 5 6.90 intv cc (v) 6.95 7.00 7.05 7.10 7.15 7.20 15 10 20 25 35 30 40 3783 g16 150c 25c C50c temperature (c) C50 47.8 soft-start current (a) 48.0 48.4 48.6 48.8 50.0 49.8 49.2 0 50 3783 g17 48.2 49.4 49.6 49.0 100 150 capacitance (nf) 0 time (ns) 40 50 60 20 3783 g18 30 20 0 5 10 15 10 80 70 gate tr gate tf frequency vs temperature maximum v sense vs temperature i sense vs temperature intv cc load regulation intv cc line regulation intv cc load regulation over temperature intv cc line regulation vs temperature i ss soft-start current vs temperature gate rise/fall time vs capacitance t a = 25c unless otherwise speci? ed
ltc3783 7 3783fb pin functions fbn (pin 1): error ampli? er inverting input/negative cur- rent sense pin. in voltage mode (v fbp v vref ), this pin senses feedback voltage from either the external resistor divider across v out for output voltage regulation, or the grounded sense resistor under the load for output current regulation. in constant current/constant voltage mode (v fbp > 2.5v), connect this pin to the negative side of the current-regulating resistor. nominal voltage for this pin in regulation is either v fbp or (v fbp C 100mv) for v ilim = 1.23v, depending on operational mode (voltage or constant cur- rent/constant voltage) set by the voltage at v fbp . fbp (pin 2): error ampli? er noninverting input/positive current sense pin. this pin voltage determines the control loops feedback mode (voltage or constant current/constant voltage), the threshold of which is approximately 2v. in voltage mode (v fbp v ref ), this pin represents the desired voltage which the regulated loop will cause fbn to follow. in constant current/constant voltage mode (v fbp > 2.5v), connect this pin to the positive side of the load current- sensing resistor. the acceptable input ranges for this pin are 0v to 1.23v (voltage mode) and 2.5v to 36v (constant current/constant voltage mode). i lim (pin 3): current limit pin. sets current sense resis- tor offset voltage (v fbp C v fbn ) in constant current mode regulation (i.e., when v fbp > 2.5v). offset voltage is 100mv when v ilim = 1.23v and decreases proportionally with v ilim . nominal voltage range for this pin is 0.1v to 1.23v. v ref (p in 4): reference voltage pin. provides a buffered version of the internal bandgap voltage, which can be connected to fbp either directly or with attenuation. nominal voltage for this pin is 1.23v. this pin should never be bypassed by a capacitor to gnd. instead, a 10k resistor to gnd should be used to lower pin impedance in noisy systems. freq (pin 5): a resistor from the freq pin to ground programs the operating frequency of the chip. the nominal voltage at the freq pin is 0.615v. sync (pin 6): this input allows for synchronizing the op- erating frequency to an external clock and has an internal 100k pull-down resistor. pwmin (pin 7): pwm gate driver input. internal 100k pull-up resistor. while pwmin is low, pwmout is low, gate stops switching and the external i th network is disconnected, saving the i th state. pwmout (pin 8): pwm gate driver output. used for con- stant current dimming (led load) or for output disconnect (step-up power supply). gate (pin 9): main gate driver output for the boost converter. intv cc (pin 10): internal 7v regulator output. the main and pwm gate drivers and control circuits are powered from this voltage. decouple this pin locally to the ic ground with a minimum of 4.7f low esr ceramic capacitor. v in (pin 11): main supply pin. must be closely decoupled to ground. sense (pin 12): current sense input for the control loop. connect this pin to the drain of the main power mosfet for v ds sensing and highest ef? ciency for v sense 36v. alternatively, the sense pin may be connected to a resistor in the source of the main power mosfet. internal leading- edge blanking is provided for both sensing methods. ss (pin 13): soft-start pin. provides a 50a pull-up current, enabled and reset by run, which charges an optional external capacitor. this voltage ramp translates into a corresponding current limit ramp through the main mosfet. ov/fb (pin 14): overvoltage pin/voltage feedback pin. in voltage mode (v fbp v ref ), this input, connected to v out through a resistor network, sets the output voltage at which gate switching is disabled in order to prevent an overvoltage situation. nominal threshold voltage for the ov pin is 1.32v (v ref + 7%) with 20mv hysteresis. in current/voltage mode (v fbp > 2.5v), this pin senses v out through a resistor divider and brings the loop into voltage regulation such that pin voltage approaches v ref = 1.23v, provided the loop is not regulating the load current (e.g., [v fbp C v fbn ] < 100mv for i lim = 1.23v).
ltc3783 8 3783fb block diagram pin functions i th (pin 15): error ampli? er output/compensation pin. the current comparator input threshold increases with this control voltage, which is the output of the g m type error ampli? er. nominal voltage range for this pin is 0v to 1.40v. run (pin 16): the run pin provides the user with an ac- curate means for sensing the input voltage and program- ming the start-up threshold for the converter. the falling run pin threshold is nominally 1.248v and the comparator has 100mv hysteresis for noise immunity. when the run pin is grounded, the ic is shut down and the v in supply current is kept to a low value (20a typ). exposed pad (pin 17): ground pin. solder to pcb ground for electrical contact and rated thermal performance. osc v-to-i v-to-i ldo bias and start-up 9 + C C + C logic v ref bias slope comp temp sensor (165c) ot ss_reset q 0.615v freq gate 12 sense 8 pwmout 11 v in 16 run 3738 bd uv itrip 17 gnd 4 v ref s r ov clk sleep en ov/fb v ref 1 s 0 5 sync 6 i lim 3 fbp fbn 2 1 ov/fb 14 ss 13 + C 50ma 0.2v + C + C imax 0.15v + C v ref + C 1.9v ivmode v ref + C i th 15 pwmin 7 2.23v v ref + C intv cc 10 a ea
ltc3783 9 3783fb operation main control loop the ltc3783 is a constant frequency, current mode con- troller for pwm led as well as dc/dc boost, sepic and ? yback converter applications. in constant current led applications, the ltc3783 provides an especially wide pwm dimming range due to its unique switching scheme, which allows pwm pulse widths as short as several converter switching periods. for voltage feedback circuit operation (de? ned by v fbp 1.23v), please refer to the block diagram of the ic and the typical application on the ? rst page of this data sheet. in normal operation with pwmin high, the power mosfet is turned on (gate goes high) when the oscillator sets the pwm latch, and is turned off when the itrip current comparator resets the latch. based on the error voltage represented by (v fbp C v fbn ), the error ampli? er output signal at the i th pin sets the itrip current comparator input threshold. when the load current increases, a fall in the fbn voltage relative to the reference voltage at fbp causes the i th pin to rise, causing the itrip current comparator to trip at a higher peak inductor current value. the average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. when pwmin goes low, pwmout goes low, the i th switch opens and gate switching is disabled. lowering pwmout and disabling gate causes the output capacitor c out to hold the output voltage constant in the absence of load current. opening the i th switch stores the correct load current value on the i th capacitor c ith . as a result, when pwmin goes high again, both i th and v out are instantly at the appropriate levels. in voltage feedback operation, an overvoltage compara- tor, ov, senses when the ov/fb pin exceeds the reference voltage by 7% and provides a reset pulse to the main rs latch. because this rs latch is reset-dominant, the power mosfet is actively held off for the duration of an output overvoltage condition. for constant current/constant voltage regulation operation (de? ned by v fbp > 2.5v), please refer to the block diagram of the ic and figure 11. loop operation is similar to the voltage feedback, except fbp and fbn now sense the voltage across sense resistor r l in series with the load. the i th pin now represents the error from the desired dif- ferential set voltage, from 10mv to 100mv, for i lim values of 0.123v to 1.23v. that is, with v ilim = 1.23v, the loop will regulate such that v fbp C v fbn = 100mv; lower values of i lim attenuate the difference proportionally. pwmin is still functional as above, but will only work properly if load current can be disconnected by the pwmout signal. in constant current/constant voltage operation, the ov/fb pin becomes a voltage feedback pin, which causes the loop to regulate such that v ov/fb = 1.23v, provided the above current-sense voltage is not reached. in this way, the loop regulates either voltage or current, whichever parameter hits its preset limit ? rst. the nominal operating frequency of the ltc3783 is pro- grammed using a resistor from the freq pin to ground and can be controlled over a 20khz to 1mhz range. in addition, the internal oscillator can be synchronized to an external clock applied to the sync pin and can be locked to a frequency between 100% and 130% of its nominal value. when the sync pin is left open, it is pulled low by an internal 100k resistor. with no load, or an extremely light one, the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. the run pin controls whether the ic is enabled or is in a low current shutdown state. a micropower 1.248v refer- ence and run comparator allow the user to program the supply voltage at which the ic turns on and off (the run comparator has 100mv of hysteresis for noise immunity). with the run pin below 1.248v, the chip is off and the input supply current is typically only 20a.
ltc3783 10 3783fb operation the ss pin provides a soft-start current to charge an external capacitor. enabled by run, the soft-start current is 50a, which creates a positive voltage ramp on v ss to which the internal i th is limited, avoiding high peak currents on start-up. once v ss reaches 1.23v, the full i th range is established. the ltc3783 can be used either by sensing the voltage drop across the power mosfet or by connecting the sense pin to a conventional shunt resistor in the source of the power mosfet, as shown in the typical application on the ? rst page of this data sheet. sensing the voltage across the power mosfet maximizes converter ef? ciency and minimizes the component count, but limits the out- put voltage to the maximum rating for this pin (36v). by connecting the sense pin to a resistor in the source of the power mosfet, the user is able to program output voltages signi? cantly greater than 36v, limited only by other components breakdown voltages. externally synchronized operation when an external clock signal drives the sync pin at a rate faster than the chips internal oscillator, the oscillator will synchronize to it. when the oscillators internal logic circuitry detects a synchronizing signal on the sync pin, the internal oscillator ramp is terminated early and the slope compensation is increased by approximately 25%. as a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the ic be programmed to be about 80% of the external clock frequency. attempting to synchronize to too high an external frequency (above 1.3f osc ) can result in inad- equate slope compensation and possible subharmonic oscillation (or jitter). the external clock signal must exceed 2v for at least 25ns, and should have a maximum duty cycle of 80%, as shown in figure 1. the mosfet turn-on will synchronize to the rising edge of the external clock signal. programming the operating frequency the choice of operating frequency and inductor value is a tradeoff between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet and diode switching losses. however, lower frequency operation requires more inductance for a given amount of load current. the ltc3783 uses a constant frequency architecture that can be programmed over a 20khz to 1mhz range with a single external resistor from the freq pin to ground, as shown in the application on the ? rst page of this data sheet. the nominal voltage on the freq pin is 0.615v, and the current that ? ows out of the freq pin is used to charge and discharge an internal oscillator capacitor. the oscillator frequency is trimmed to 300khz with r t = 20k. a graph for selecting the value of r t for a given operating frequency is shown in figure 2. 3783 f01 2v to 7v mode/ sync gate i l t min = 25ns 0.8t d = 40% t t = 1/f o figure 1. mode/sync clock input and switching waveforms for synchronized operation frequency (khz) 10 r t (k) 100 1 100 1000 10000 3783 g09 1 10 1000 figure 2. timing resistor (r t ) value
ltc3783 11 3783fb operation intv cc regulator bypassing and operation an internal, p-channel low dropout voltage regulator pro- duces the 7v supply which powers the gate drivers and logic circuitry within the ltc3783 as shown in figure 3. the intv cc regulator can supply up to 50ma and must be bypassed to ground immediately adjacent to the ic pins with a minimum of 4.7f low esr or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. for input voltages that dont exceed 8v (the absolute maximum rating for intv cc is 9v), the internal low dropout regulator in the ltc3783 is redundant and the intv cc pin can be shorted directly to the v in pin. with the intv cc pin shorted to v in , however, the divider that programs the regulated intv cc voltage will draw 15a from the input sup- ply, even in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . regardless of whether the intv cc pin is shorted to v in or not, it is always necessary to have the driver circuitry bypassed with a 4.7f low esr ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. as a result, high input voltage applications in which a large power mosfet is being driven at high frequencies can cause the ltc3783 to exceed its maximum junction temperature rating. the junction temperature can be estimated using the following equations: i q(tot) = i q + f ? q g p ic = v in ? (i q + f ? q g ) t j = t a + p ic ? ja the total quiescent current i q(tot) consists of the static supply current (i q ) and the current required to charge and discharge the gate of the power mosfet. the 16-lead fe package has a thermal resistance of ja = 38c/w and the dhd package has an ja = 43c/w as an example, consider a power supply with v in = 12v and v out = 25v at i out = 1a. the switching frequency is 300khz, and the maximum ambient temperature is 70c. the power mosfet chosen is the si7884dp , which has a maximum r ds(on) of 10m (at room temperature) and C + 1.230v r2 r1 p-ch 7v driver gate c vcc 4.7f x5r c in input supply 6v to 36v gnd place as close as possible to device pins m1 3783 f03 intv cc v in gnd logic 6v-rated power mosfet figure 3. bypassing the ldo regulator and gate driver supply
ltc3783 12 3783fb operation a maximum total gate charge of 35nc (the temperature coef? cient of the gate charge is low). i q(tot) = 1.2ma + 35nc ? 300khz = 12ma p ic = 12v ? 12ma = 144mw t j = 70c + 110c/w ? 144mw = 86c this demonstrates how signi? cant the gate charge current can be when compared to the static quiescent current in the ic. to prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high v in . a tradeoff between the operating frequency and the size of the power mosfet may need to be made in order to maintain a reli- able ic junction temperature. prior to lowering the operat- ing frequency, however, be sure to check with the power mosfet manufacturers for the latest low q g , low r ds(on) devices. power mosfet manufacturing technologies are continually improving, with newer and better-performing devices being introduced almost monthly. output voltage programming in constant voltage mode, in order to regulate the output voltage, the output voltage is set by a resistor divider ac- cording to the following formula: vv r r out fbp ?1 2 1 where 0 v fbp 1.23v. the external resistor divider is connected to the output as shown in figure 4, allowing remote voltage sensing. the resistors r1 and r2 are typically chosen so that the error caused by the 500na input bias current ? owing out of the fbn pin during normal operation is less than 1%, which translates to a maximum r1 value of about 25k at v fbp = 1.23v. for lower fbp voltages, r1 must be reduced accordingly to maintain accuracy, e.g., r1 < 2k for 1% accuracy when v fbp = 100mv. more accuracy can be achieved with lower resistances, at the expense of increased dissipation and decreased light load ef? ciency. a similar analysis applies to the v fbp resistive divider, if one is used: vv r rr fbp ref ? 3 34 where r3 is subject to a similar 500na bias current. ltc3783 r4 r3 run pwmin i th ss v ref fbp fbn freq sync v in ov/fb pwmout i lim gate sense intv cc gnd v in 3v to 36v gnd v out r2 r1 3783 f04 figure 4. ltc3783 boost application programming turn-on and turn-off thresholds with the run pin the ltc3783 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in figure 5. this allows users to accurately program an input voltage at which the converter will turn on and off. the falling threshold on the run pin is equal to the internal reference voltage of 1.248v. the comparator has 100mv of hysteresis to increase noise immunity. the turn-on and turn-off input voltage thresholds are programed using a resistor divider according to the fol- lowing formulas: vv r r vv in off in on () () .? .? 1 248 1 2 1 1 348 1 1 2 1 r r the resistor r1 is typically chosen to be less than 1m.
ltc3783 13 3783fb operation for applications where the run pin is only to be used as a logic input, the user should be aware of the 7v absolute maximum rating for this pin! the run pin can be con- nected to the input voltage through an external 1m resistor, as shown in figure 5c, for always on operation. soft-start capacitor selection for proper soft-start operation, the ltc3783 should have a suf? ciently large soft-start capacitor, c ss , attached to the ss pin. the minimum soft-start capacitor size can be estimated on the basis of output voltage, capacitor size and load current. in addition, pwm operation reduces the effective ss capacitor value by the dimming ratio. c gratio a c v r ss min out out ds () ( ?dimmin ? ? ? ? 250 o on sense mv v )/ ?. 150 1 2 assuming 50% ripple current, where r ds(on)/sense represents either the r ds(on) of the switching mosfet or r sense , whichever is used on the sense pin. dimming ratio is described by 1/d pwm as shown in figure 6. application circuits a basic ltc3783 pwm-dimming led application is shown on the ? rst page of this data sheet. operating frequency and pwm dimming ratio the minimum operating frequency, f osc , required for proper operation of a pwm dimming application depends on the minimum pwm frequency, f pwm , the dimming ratio 1/d pwm , and n, the number of f osc cycles per pwm cycle: f nf d osc pwm pwm ? C + run comparator v in run r2 r1 input supply optional filter capacitor + C gnd 3783 f05a bias and start-up control 1.248v power reference 6v figure 5a. programming the turn-on and turn-off thresholds using the run pin C + run comparator 1.248v 3483 f05b run 6v external logic control figure 5b. on/off control using external logic C + run comparator v in run r2 1m input supply + C gnd 1.248v 3483 f05c 6v figure 5c. external pull-up resistor on run pin for always on operation
ltc3783 14 3783fb operation figure 6 illustrates these various quantities in relation to one another. typically, in order to avoid visible ? icker, f pwm should be greater than 120hz. assuming inductor and capacitor sizing which is close to discontinuous operation, 2 f osc cycles are suf? cient for proper pwm operation. thus, within the 1mhz rated maximum f osc , a dimming ratio of 1/d pwm = 3000 is possible. the output current needs to be re? ected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i i d in max out max max () () C 1 the peak input current is: i i d in peak out max max () () ? C 1 21 the maximum duty cycle, d max , should be calculated at minimum v in . boost converter: ripple current i l and the factor the constant in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. for example, if 30% ripple current is chosen, then = 0.3, and the peak current is 15% greater than the average. for a current mode boost regulator operating in ccm, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. for the ltc3783, this ramp compensation is internal. having an internally ? xed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. if too large an inductor is used, the resulting current ramp ( i l ) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). if too small an inductor is used, but the converter is still operating in ccm (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. to ensure good current mode gain and to avoid subharmonic oscillation, it is recom- mended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. for example, if the maximum average input current is 1a, choose a i l between 0.2a and 0.4a, and correspondingly a value between 0.2 and 0.4. boost converter: duty cycle considerations for a boost converter operating in a continuous conduction mode (ccm), the duty cycle of the main switch is: d vvv vv out d in out d C where v d is the forward voltage of the boost diode. for converters where the input voltage is close to the output voltage, the duty cycle is low, and for converters that develop a high output voltage from a low input voltage, the duty cycle is high. the maximum output voltage for a boost converter operating in ccm is: v v d v out max in min max d () () C C 1 the maximum duty cycle capability of the ltc3783 is typically 90%. this allows the user to obtain high output voltages from low input supply voltages. boost converter: the peak and average input currents the control circuit in the ltc3783 is measuring the input current (either by using the r ds(on) of the power mosfet or by using a sense resistor in the mosfet source), so pwmin gate 3783 f06 # = n d pwm /f pwm 1/f pwm 1/f osc figure 6. pwm dimming parameters
ltc3783 15 3783fb operation boost converter: inductor selection given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: l v if d where i i in min l max l out () ( ? ? : ? m max max d ) C 1 remember that most boost converters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short- circuit protected, please refer to the applications section covering sepic converters. the minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: i i d l sat out max max () () ? C 1 21 the saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. boost converter: operating in discontinuous mode discontinuous mode operation occurs when the load cur- rent is low enough to allow the inductor current to run out during the off-time of the switch, as shown in figure 7. once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1mhz to 10mhz. if the off-time is long enough, the drain voltage will settle to the input voltage. depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power mosfet to go below ground where it is clamped by the body diode. this ringing is not harmful to the ic and it has not been shown to contribute signi? cantly to emi. any attempt to damp it with a snubber will degrade the ef? ciency. boost converter: power mosfet selection the power mosfet can serve two purposes in the ltc3783: it represents the main switching element in the power path, and its r ds(on) can represent the current sensing element for the control loop. important parameters for the power mosfet include the drain-to-source breakdown voltage bv dss , the threshold voltage v gs(th) , the on-resistance r ds(on) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges q gs and q gd , respectively, the maximum drain current i d(max) and the mosfets thermal resistances jc and ja . the gate drive voltage is set by the 7v intv cc low drop regulator. consequently, 6v rated mosfets are required in most high voltage ltc3783 applications. if low input voltage operation is expected (e.g., supplying power from a lithium-ion battery or a 3.3v logic supply), then sublogic-level threshold mosfets should be used. pay close attention to the bv dss speci? cations for the mosfets relative to the maximum actual switch voltage in the ap- plication. many logic-level devices are limited to 30v or less, and the switch node can ring during the turn-off of the mosfet due to layout parasitics. check the switching waveforms of the mosfet directly across the drain and source terminals using the actual pc board layout for excessive ringing. output voltage 200mv/div inductor current 1a/div 1s/div 3783 f07 mosfet drain voltage 20v/div figure 7. discontinuous mode waveforms
ltc3783 16 3783fb operation during the switch on-time, the imax comparator limits the absolute maximum voltage drop across the power mosfet to a nominal 150mv, regardless of duty cycle. the peak inductor current is therefore limited to 150mv/r ds(on) . the relationship between the maximum load current, duty cycle, and the r ds(on) of the power mosfet is: rmv d i ds on max out max t () () ? C ?? 150 1 1 2 the t term accounts for the temperature coef? cient of the r ds(on) of the mosfet, which is typically 0.4%/c. figure 8 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. it is worth noting that the 1 - d max relationship between i o(max) and r ds(on) can cause boost converters with a wide input range to experience a dramatic range of maxi- mum input and output currents. this should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply, and also to avoid triggering the 150mv imax comparator, as this condition can result in excessive noise. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current, and the junction temperature itself (due to the positive temperature coef? cient of its r ds(on) . as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the controller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case speci? cations for v sense(max) and the r ds(on ) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a boost converter is: p i d rd fet out max max ds on max t () () C ??? 1 2 kv i d cf out out max max rss ?? C ?? . () 185 1 the ? rst term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. junction temperature (c) C50 r t normalized on resistance 1.0 1.5 150 3783 f08 0.5 0 0 50 100 2.0 figure 8. normalized r ds(on) vs temperature another method of choosing which power mosfet to use is to check what the maximum output current is for a given r ds(on) , since mosfet on-resistances are available in discrete values. imv d r omax max ds on t () () ? C ?? 150 1 1 2
ltc3783 17 3783fb operation from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? ja the ja to be used in this equation normally includes the jc for the device plus the thermal resistance from the case to the ambient temperature ( ca ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. boost converter: output diode selection to maximize ef? ciency, a fast switching diode with low forward drop and low reverse leakage is desired. the output diode in a boost converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. ii i d d peak l peak out max ma ()() () ? C 1 21 x x the power dissipated by the diode is: p d = i out(max) ? v d and the diode junction temperature is: t j = t a + p d ? ja the ja to be used in this equation normally includes the jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dissipation. boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. the effects of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform are illustrated in figure 9 for a typical boost converter. v out (ac) $ v esr ringing due to total inductance (board + cap) $ v cout 3783 f09 figure 9. output ripple voltage the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging v. this percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modi? ed. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the fol- lowing equation: esr v i where i cout out in peak in peak 001 1 .? : () () 21 ? C () i d out max max for the bulk c component, which also contributes 1% to the total ripple: c i vf out out max out () .? ? 001
ltc3783 18 3783fb operation for many designs it is possible to choose a single capacitor type that satis? es both the esr and bulk c requirements for the design. in certain demanding applications, however, the ripple voltage can be improved signi? cantly by con- necting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr setup, while an electrolytic capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be veri? ed on a dedicated pc board (see board layout section for more information on component place- ment). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look signi? cantly worse than they would be on a properly designed pc board. the output capacitor in a boost regulator experiences high rms ripple currents. the rms output capacitor ripple current is: ii vv v rms cout out max out in min in min () () () ( ;? C ) ) note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and hence, the input current waveform is continuous (see figure 10). the input volt- age source impedance determines the size of the input capacitor, which is typically in the range of 10f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. i in i l 3783 f10 figure 10. inductor and input currents the rms input capacitor ripple current for a boost converter is: i v lf d rms cin in min max () () ;.? ? ? 03 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter, and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! boost converter design example the design example given here will be for the circuit shown in figure 1. the input voltage is 12v, and the output voltage is 25v at a maximum load current of 0.7a (1a peak). 1. the duty cycle is: d vvv vv out d in out d C .C . % 25 0 4 12 25 0 4 53 2. the operating frequency is chosen to be 1mhz to maximize the pwm dimming range. from figure 2, the resistor from the freq pin to ground is 6k. 3. an inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: i i d in peak out max max () () ? C .? . 1 21 12 0 7 7 1053 18 C. . a the inductor ripple current is: = = = i i d a l out max max ?.? . . . () 1 04 07 1053 06
ltc3783 19 3783fb operation and so the inductor value is: l v if d v amhz h in min l max () ? ? .? ?. 12 06 1 053 11 4. r sense should be: r v i mv sense sense max in peak 05 0 5 150 1 .? .? . () () 8 8 42 a m 5. the diode for this design must handle a maximum dc output current of 0.7a and be rated for a minimum reverse voltage of v out , or 25v. a 1a, 40v diode from zetex was chosen for its speci? cations, especially low leakage at higher temperatures, which is important for maintaining dimming range. 6. voltage and value permitting, the output capacitor usu- ally consists of some combination of low esr ceramics. based on a maximum output ripple voltage of 1%, or 250mv, the bulk c needs to be greater than: c i vf a vmhz out out max out () .? ? . .? ? 001 07 001 25 1 3f the rms ripple current rating for this capacitor needs to exceed: ii vv v rms cout out max out in min in min () () () () ? C 0 07 25 12 12 07 .? C . a vv v a based on value and ripple current, and taking physical size into account, a surface mount ceramic capacitor is a good choice. a 4.7f tdk c5750x7r1h475m will satisfy all requirements in a compact package. 7. the soft-start capacitor should be: c gratio a c v r ss min out out ds () ( ?dimmin ? ? ? ? 250 o on sense mv v afv )/ ?. ?? ?.?? 150 1 2 2 3000 50 4 7 25 ? 4 42 150 1 2 8 m mv v f ?. 8. the choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. for this particular design and lab setup, 20f was found to be satisfactory. pc board layout checklist 1. in order to minimize switching noise and improve out- put load regulation, the gnd pad of the ltc3783 should be connected directly to 1) the negative terminal of the intv cc decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom terminals of the sense resistors or the source of the power mosfet, 4) the negative terminal of the input capacitor, and 5) at least one via to the ground plane immediately under the exposed pad. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resistance and inductance. 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground plane is to be used for high dc currents, choose a path away from the small-signal components. 3. place the c vcc capacitor immediately adjacent to the intv cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate-drive currents. a low esr and esl 4.7f ceramic capacitor works well here. 4. the high di/dt loop from the bottom terminal of the output capacitor, through the power mosfet, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase hf noise on the output. if low esr ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum.
ltc3783 20 3783fb operation 5. check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing which can exceed the maximum speci? ed voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power mosfet. 6. place the small-signal components away from high frequency switching nodes. all of the small-signal com- ponents should be placed on one side of the ic and all of the power components should be placed on the other. this also allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents ? ow out of the ic ground pad in one direction (to bottom plate of the intv cc decoupling capacitor) and small-signal currents ? ow in the other direction. 7. if a sense resistor is used in the source of the power mosfet, minimize the capacitance between the sense pin trace and any high frequency switching nodes. the ltc3783 contains an internal leading-edge blanking time of approximately 160ns, which should be adequate for most applications. 8. for optimum load regulation and true remote sensing, the top of the output resistor should connect indepen- dently to the top of the output capacitor (kelvin connec- tion), staying away from any high dv/dt traces. place the divider resistors near the ltc3783 in order to keep the high impedance fbn node short. 9. for applications with multiple switching power convert- ers connected to the same input supply, make sure that the input ? lter capacitor for the ltc3783 is not shared with any other converters. ac input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the ltc3783. a few inches of pc trace or wire (l ~ 100nh) between the c in of the ltc3783 and the actual source v in should be suf? cient to prevent current-sharing problems. returning the load to v in : a single inductor buck-boost application as shown in figure 11, due to its available high side current sensing mode, the ltc3783 is also well-suited to a boost converter in which the load current is returned to v in , hence providing a load voltage (v out C v in ) which can be greater or less than the input voltage v in . this con? guration allows for complete overlap of input and output voltages, with the disadvantages that only the load current, and not the load voltage, can be tightly regulated. the switch must be rated for a v ds(max) equal to v in + v load . the design of this circuit resembles that of the boost converter above, and the procedure is much the same, except v out is now (v in + v load ), and the duty cycles and voltages must be adjusted accordingly. ltc3783 run pwmin i th ss v ref fbp fbn freq sync v in ov/fb pwmout i lim gate sense intv cc gnd v in 9v to 26v r l 0.28 v out led string 1-4 ea lumileds lhxl-bw02 each led is 3v to 4.2v at 350ma 10f, 50v c5750x7r1h106m ceramic 0v to 1.23v 10f, 50v s 2 umk432c106mm 10h sumida cdrh8d28-100 gnd 3783 f11 1m 20k pmeg6010 fairchild fdn5630 1k 40.2k 4.7f 100k pwm 5v at 0hz to 10hz 4.7f 0.05 1f figure 11. single inductor buck-boost application with analog dimming and low frequency pwm dimming
ltc3783 21 3783fb operation similar to the boost converter, which can be dimmed via the digital pwmin input or the analog fbp pin, the buck- boost can be dimmed via the pwmin pin or the analog i lim pin, which adjusts the offset voltage to which the loop will drive (v fbp C v fbn ). in the case of the buck-boost, however, the dimming ratio cannot be as high as in the boost converter, since there is no load switch to preserve the v out level while pwmin is low. using the ltc3783 for buck applications as shown in figure 12, high side current sensing also al- lows the ltc3783 to control a functional buck converter when load voltage is always suf? ciently less than v in . in this scheme the input voltage to the inductor is lowered by the load voltage. the boost converter now sees a v in = v in C v load , meaning the controller is now boosting from (v in C v load ) to v in . ltc3783 run pwmin i th ss v ref fbp fbn freq sync v in ov/fb pwmout i lim gate sense intv cc gnd v in 6v to 36v led string gnd 3783 f12 figure 12. led buck application
ltc3783 22 3783fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dhd package 16-lead plastic dfn (5mm 4mm) (reference ltc dwg # 05-08-1707) 4.00 p 0.10 (2 sides) 5.00 p 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjgd-2) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 2.44 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ r = 0.20 typ 4.34 p 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dhd16) dfn 0504 0.25 p 0.05 pin 1 notch 0.50 bsc 4.34 p 0.05 (2 sides) recommended solder pad pitch and dimensions 2.44 p 0.05 (2 sides) 3.10 p 0.05 0.50 bsc 0.70 p 0.05 4.50 p 0.05 package outline 0.25 p 0.05
ltc3783 23 3783fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 p 0.05 0.65 bsc 4.50 p 0.10 6.60 p 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3783 24 3783fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0208 ? printed in usa related parts part number description comments lt ? 1618 monolithic 1.4mhz boost regulator constant-current/constant-voltage, 1a switch ltc1871 boost, flyback, sepic controller no r sense , 2.5v v in 36v, 92% duty cycle lt3477 3a dc/dc led driver with rail-to-rail current sense 2.5v v in 25v: buck, buck-boost and boost topologies ltc3780 high power buck-boost controller 4-switch, 4v v in 36v, 0.8v v out 30v ltc3782 2-phase boost controller high power, 6v v in 40v, 150khz to 500khz ltc3827/ltc3827-1 low i q current dual controllers 2-phase, 80a i q , 0.8v v out 10v, 4v v in 36v ltc4002 standalone 2a li-ion battery charger 1- and 2-cell, 4.7v v in 22v, 3 hour timer

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